Bihar Engineering University previous year question solution . BEU previous year question pdf. BEU question paper digital electronics. BEU pyq solution . DIGITAL ELECTRONICS 2022 QUESTION PAPER SOLUTION. Electrical engineering 4 semester question paper and solution.
(a) What is the next number in the following octal counting sequence? 724, 725, 726, 727,
(b) What do you mean by a positive logic system and a negative logic system?
(c) Subtract using 9’s complement : 745.81 436.62
(d) The following operation is correct for at least one number system. Find the correct number system: 1234+5432=6666
(e) What is a tri-state logic?
(f) Which are the fastest logic family and the slowest logic family?
(g) Which memory technology needs the least power?
(h) What is a register? What is a shift register?
(i) What is a master-slave flip-flop?
(j) Fill in the blank : (100101000111) (BCD) = (-)10
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2 (a) Which of the following are analog quantities and which are digital? Number of atoms in a sample of material, Altitude of an aircraft, Pressure in a bicycle tire, Current through a speaker, and Timer setting on a microwave oven.
(b) What do you mean by self-comple- menting code? Write two self-comple- menting codes.
(c) If the waveforms A and B shown in Fig. 1 are applied to a two-input XOR gate, determine the output waveform
3. (a) Perform the following in excess-3 code using the 10’s complement method :239-597013 95
(b) Design and implement a 4-bit binary to Gray converter.
(c) Reduce the following expression using K-map and implement it in AOI logic as well as in NOR logic :F = IIM (0, 1, 2, 3, 4, 7)
4 . (a) Reduce the following expression and implement it using universal logic gate:Em (1, 5, 6, 12, 13, 14)+d(2, 4)
(b) Use a multiplexer to implement the logic function F = ABC.
Q5. (a) Determine the Q-output waveform if the inputs shown in Fig. 2 are applied to the gated D-latch which is initially RESET :
(b) Design the conversion circuit for S-R flip-flop to J-K flip-flop.
6. (a) What in basic difference between a counter and a shift register?
(b) With neat diagrams, explain the working of the following types of shift registers :
(i) Serial-in, serial-out
(ii) Serial-in, parallel-out
(c) Design and implement mod-10 a asynchronous counter using T flip-flops
7. (a) Design and implement a synchronous 3-bit up/down counter using J-K flip-flops.
(b) Determine the resolution of-
(i) 6-bit DAC (ii) 12-bit DAC in terms of percentage.
(c) What is the resolution of a 9-bit DAC which uses a ladder network? What is this resolution expressed as a percentage? If the full-scale output voltage of this converter is +5 V, what is resolution in volts?
8. (a) For the 4-bit weighted resistor DAC shown in Fig. 3, determine the-
(i) weight of each input bit if theinputs are 0 V and 5 V;
(ii) full-scale output if R_{f} = R = 1 kn.Also, find the full-scale output if Rf ischanged to 500 :
(b) What is a PLD? What do ‘x’ and ‘dot’ represent on a PLD diagram?
9.(a) What are the different technologies usedfor the fabrication of ROM memories?Determine how many 16K * 4 memory circuits would be required to constructeach of the following memories :(i) 256K * 8(ii) 128K * 16
(b) Define Memory cell, Address and Byte.(c) Using the simplified connection formatof a PLA, show how an 8 * 1 PROM should be programmed to implementthe logic function
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