BEU Digital CMOS VLSI design question paper solution 2022

Bihar engineering university ECE Branch pyq solution. Digital cmos vlsi design solution 2022 . BEU previous year question solution.

(a) Why is NMOS technology preferred more than PMOS technology?
(b) What is the output when both nMOS and PMOS transistors of CMOS logic gates are under ON condition?
(c) How do you prevent latch up problem in CMOS?
(d) List the basic process for IC fabrication.
(e) Define RC delay model.
(f) What are the advantages of CMOS process?

(g) Name advantages and disadvantages pass-transistors.
(h) What is channel-length modulation?
(i) Define threshold voltage in CMOS.
(j) What is body effect?

2. (a)Draw suitable energy band diagram of p-type of silicon and explain. Defin work-function and derive the relation
(b) State the types of scaling an differentiate.

3. (a) Derive CMOS the characteristics inverter and obtain relationship for output voltage D th a different regions in the transfe characteristics.
(b) Write the threshold voltage equatior with brief explanation.

4.(a) Explain various fabrication steps with neat of CMOS diagrams. Compare the CMOS and BiCMOS

(b) Explain
(i) Why is metal-metal spacing larger than poly-poly spacing?
(ii) What are the effects of scaling of Vt?

5. (a) Design a circuit using CMOS inverter circuit that implements the function F=A+BC.
(b) What are different layout design rules? Explain them with suitable examples. What are ‘wires’ and ‘vias? How to design them?

6. (a) Explain the delay in combinational logic network and how combinational delay can be reduced. What are various switch logic circuits? Compare their merits and demerits.
(b) Explain the concept of MOSFET as switches.

7. (a) Derive expression an conductance (9m) of an for trans- N-channel MOSFET operating in linear and saturation regions.
(b) What are the various properties of transmission gate logic?

8.(a) Determine Zpu/Zpd for NMOS inverter driven by another inverter.
(b) What is SOI? What is the material used as an insulator and why?

9. Write notes on the following:
(a) CMOS D-Latch
(b) Switching power dissipation in CMOS

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