BEU Computer Organization and Architecture Question paper solution

BEU Computer Organization and Architecture Question paper solution:– BEU ECE 6 semester computer organization question paper with solution. Bihar engineering university. previous year question ECE branch all semester BEU computer organization 2022 solution.

(a) One byte equals to how many bits?
(i) 4 bits
(ii)8 bits
(iii) 12 bits
(iv) 16 bits


(b) Which among the following is volatile?
(i) ROM
(4) EPROM
(iii) DROM
(iv) RAM

(c) The intra-data transfer techniques are implemented using
(i) serial i/o
(ii) parallel i/o
(iii) Both (i) and (u)
(iv) Neither (1) nor (2)


(d) A 5-stage pipeline with the stages taking 1. 1, 3, 1. 1 units of time has a throughput of
(i) 1/3
(ü) 1/7
(iii) 7
(w) 3


(e) Which memory unit has lowest access time?
(i) Cache
(ii) Registers
(iii) Magnetic disk
(iv) Main memory


(f)The instruction, Add #45, R1 does
(i) adds the value of 45 to the address of R1 and stores 45 in that address
(ii) adda 45 to the value of R1 and stores it in RI
(iii) find the memory location 45 and adds that content to that of RI
(iv) None of the above

(g) A certain processor uses a fully associative cache of size 16 KB. The cache block size is 16 bytes Assume that the main memory is byte addressable and uses a 32-bit address How many bits are required for the Tag and the Index fields respectively in the addresses generated by the processor?
(i) 24 bits and 0 bit
(ii) 28 bits and 4 bits
(iii) 24 bits and 4 bits
(iv) 28 bits and 0 bit


(h) Consider statements: the following three
81: There is an anti-dependence between instructions 12 and 15.
S2: There is anti-dependence between instructions 12 and 14.
S3: Within an instruction pipeline an anti-dependence always creates one or more stalls.
(i) Which one of the above statements is/are correct?
(i)Only S1 is true
(ii) Only s2 is true
(iii) Only s1 and s3 are true
(iv) Only s2 and s3 are true

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2. What do you mean by Direct Memory Access? Draw its block diagram and also differentiate between Burst mode DMA and Cycle stealing DMA.

3. Consider a machine with a byte addressable main memory of 216 bytes and a direct mapped data cache consisting of 32 lines of 64 bytes each. In this system, a 50 x 50 two- dimensional array of bytes is stored in the main memory starting from memory location 1100 H. Assuming the following clauses, calculate the total cache misses which will occur in the system:

(a) The data cache is initially empty

(b) The complete array is accessed twice

(c) The contents of the cache do not change in between the two accesses

4.What do you mean by address sequencing? Explain address sequencing with the help of examples and neat diagram.

5. Explain the connections between the various components of a generic computer system, as shown in the following figure:

6. With the help of neat diagrams, explain the various principles of designing pipelined processors

7. A processor has 16 integer registers (RO, R1, R15) and 64 floating point registers (FO, F1, P63). It uses a 2-byte instruction format There are four categories of instructions: Type-1, Type-2, Type-3 and Type 4 Type-1 category consists of four instructions, each with 3 integer register operands (3Rs) Type-2 category consists of eight instructions, each with 2-floating poin register operands (2Fs) Type-3 category consists of fourteen instructions, each with one integer register operand and one-floating point register operand (IR+1F) Type 4 category consists of N instructions, each with a floating point register operand (IF). Calculate the maximum value that N can attain.

8. Explain the Daisy chaining mechanism for bus arbitration. Analyze the three-bus arbitration methods-Daisy chaining, polling and independent requesting with respect to communication reliability in the event of hardware failures.

9. Differentiate between the following: 3%-4-1

(a) RISC vs. CISC

(b) Interrupta us. Exceptions

(c) Cache vs. Registers

(d) Macro us. Micro

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