Computer Architecture BEU Question Paper Solution:- In this article, I have provided the solution for Computer Architecture along with its solution based on BEU question paper. I tried to make the solutions very simple so that each and every student can understand it.
Students can easily download the solution of the Computer Architecture question paper as well as BEU Question Paper Solution by just clicking on the download button available at the bottom of this page.
This Blog is to provide BEU Solutions to past year’s question papers in Computer Architecture assisting Students in their exam preparation
Download Computer Architecture B.Tech 6th Semester 2022,
BEU PYQ (Previous Years Question) Papers
Download Bihar Engineering University (BEU) Previous Years Question Paper Solution
1. Choose the correct option of the following.
(a) In the case of the zero-address instruction method, the operands are stored in
(i) registers ✔
(ii) accumulators
(iii) push-down stack
(iv) cache
(b) The addressing mode which makes use of in-direction pointers is
(i) indirect addressing mode ✔
(ii) index addressing mode
(iii) relative addressing mode
(iv) offset addressing mode
(c) When generating physical addresses from a logical address, the offset is stored in
(i) translation look-aside buffer
(ii) relocation register ✔
(iii) page table
(iv) shift register
(d) The Boot sector files of the system are stored in
(i) Hard disk ✔
(ii) ROM
(iii) RAM
(iv) fast solid-state chips motherboard in the
(e) The transfer of large chunks of data with the involvement of the processor in done by
(i) DMA controller ✔
(ii) arbitrator
(iii) user system programs
(iv) None of the above
(f) In memory-mapped I/O
(i) The I/O devices and the memory share the same address space ✔
(ii) the 1/O devices have a separate address space
(iii) the memory and I/O devices have an associated address space
(iv) a part of the memory is specifically set aside for the 1/0 operation
(g) The return address from the interrupt-service routine is stored on the
(i) system heap
(ii) processor register
(iii) processor stack ✔
(iv) memory
(h) The resistor which is attached to the service line is called
(i) push-down resistor
(ii) pull-up resistor ✔
iii) breakdown resistor
(iv) line resistor
(i) In the micro-programmed approach, the signals are generated by
(i) machine instructions ✔
(ii) system programs
(iii) utility tools
(iv) None of the above
(j) To read the control words sequentially, is used.
(i) PC
(ii) IR
(iii) UPC ✔
(iv) None of the above
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All in one BEU PYQ Solution PDF is Provided below
2. (a) Explain the following program control instructions with the help of suitable illustrations:
(i) Branch and Jump
(ii) CALL and RETN
2. (b) How is virtual memory managed using Paging and TLB? Explain with a suitable example.
3. (a) Write a program using 8086 assembly language for interchanging the values of two memory locations.
3. (b) Discuss any five characteristics of an RISC architecture. What are the advantages of using large register files in these machines? Explain using suitable illustration.
4. (a )Explain the instruction pipeline using an illustration. What are the various problems faced by the instruction pipeline?
4. (b) What do you mean by cache memory? How does it affect the performance of the computer system? An eight-way. set-associative cache is used in a computer in which the real memory size is 232 bytes. The line size is 16 bytes and there are 2 lines per set. Calculate the cache size and tag length.
5. (a) Explain the Daisy chaining mechanism for bus arbitration. Analyze the three bus arbitration methods chaining. polling and independent requests with respect to communication reliability in the event of hardware failures.
5. (b) Give the block diagram of the micro-program sequencer for a control memory and explain it properly.
6 (a) What do you understand by hardwired control? Give various methods to design hardwired control units. Describe anyone with a suitable example.
6. (b) Explain the term ‘RAID’. What are the techniques used by RAID to enhance reliability?
7 (a) What is an array processor? Explain the SIMD array processor with a suitable example.
7. (b) A digital computer has a common bus system of 16 registers of 32 bits each. The bus is constructed with multiplexers. (i) How many selection inputs are there in each multiplexer? (ii) What size of multiplexer is needed?
8. (a) When do you say the floating-point number is normalized? Explain how the floating-point representation of numbers is done. Represent the number (+46-25) as a floating-point binary number with 32 bits.
8. (b) Explain in detail the hardware-based speculation for an MIPS processor and explain how multiple issue is handled with speculation.
9. (a) What are the pipeline conflicts? Explain the hardware techniques to handle the branch instructions.
9. (b) A DMA controller transfers 16-bit words to memory using cycle stealing. The words are assembled from a device that transmits characters at the rate of 2400 characters per second. The CPU is fetching and executing instructions at an average rate of 1 million instructions per second. By how much will the CPU be slowed down because of DMA transfer?
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